The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. Such advances have increased the complexity and challenges of processing and manufacturing of ICs.
In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while critical dimensions (i.e., the smallest components (lines, or openings) that can be created using a fabrication process) have decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down also produces a relatively high power dissipation value, which may be addressed by using low power dissipation devices such as complementary metal-oxide-semiconductor (CMOS) devices. CMOS devices have typically been formed with a gate oxide and polysilicon gate electrode. There has been a desire to replace the gate oxide and polysilicon gate electrode with a high dielectric constant (high-k) gate dielectric and metal gate electrode to improve device performance as feature sizes continue to decrease.
However, problems arise when integrating a high-k/metal gate feature in a CMOS process flow. It is within this context the following disclosure arises.